By Harry Hsieh,Felice Balarin,Alberto L. Sangiovanni-Vincentelli
ISBN-10: 079237262X
ISBN-13: 9780792372622
ISBN-10: 1461356644
ISBN-13: 9781461356646
The aim of this publication is to enquire how formal equipment should be utilized to the area of embedded approach layout. The emphasis is on the specification, illustration, validation, and layout exploration of such platforms from a high-level standpoint. The authors overview the framework upon which the theories and experiments are established, and in which the formal equipment are associated with synthesis and simulation.
a proper verification technique is formulated to ensure basic homes of the designs and display that this technique is effective in facing the matter of complexity and potent in discovering insects. even though, handbook intervention within the type of abstraction choice and separation of timing and performance is needed. It is conjectured that, for particular homes, effective algorithms exist for thoroughly computerized formal validations of structures.
Synchronous Equivalence: Formal equipment for Embedded Systems offers a new formal method of high-level equivalence research. It opens layout exploration avenues formerly uncharted. It is a piece that could stand by myself yet whilst is totally suitable with the synthesis and simulation framework defined in one other e-book via Kluwer educational Publishers Hardware-Software Co-Design of Embedded Systems: The POLIS Approach, through Balarin et al.
Synchronous Equivalence: Formal tools for Embedded Systems may be of curiosity to embedded process designers (automotive electronics, client electronics, and telecommunications), micro-controller designers, CAD builders and scholars, in addition to IP services, structure platform designers, working process services, and architects of VLSI circuits and systems.
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Synchronous Equivalence: Formal Methods for Embedded Systems by Harry Hsieh,Felice Balarin,Alberto L. Sangiovanni-Vincentelli
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